(Invited) A CMOS Inverter Technology Constructed with T-Shaped Gate Poly-Si Thin-Film Transistors

Vollständiger Abstract

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In this work, we report a novel CMOS TFT fabrication scheme with the poly-Si TFTs featuring a T-shaped gate (T-gate), air spacers, and a self-aligned lightly doped drain (LDD). The formation of the n + poly-Si T-gate is based on a unique process we developed recently [1]. Furthermore, by appropriately adjusting the implantation energy and dosage, we can achieve both LDD and heavily doped source/drain (S/D) regions with a single implantation process [2]. After the transistors are fabricated, the deposited oxide layer for passivation presses down on the wings of the T-gates, causing them to droop and naturally form air spacers on both sides of the gate electrodes. This can help reduce parasitic capacitance between the gate and S/D. As expected, the implementation of LDD can reduce the off-state leakage current for both n- and p-channel poly-Si TFTs as compared to the counterparts with the conventional gated configuration and without LDD. In the meantime, the n-channel T-gate poly-Si TFTs with LDD also exhibit a higher on-current than the conventional ones, thanks to the greatly shortened gated length [2]. Nonetheless, the on-current of the p-channel T-gate poly-Si TFTs with LDD is lowered despite the shorter gate length. Details about the mechanisms are explored in this work. Moreover, using n + poly-Si gates increases the threshold voltage (V th ) of p-channel TFTs. This issue can be addressed by adjusting channel doping. Using this approach, we have successfully fabricated CMOS inverters. Figure 1 illustrates the voltage transfer characteristics (VTC) of fabricated CMOS inverters operated at 3V, confirming full-swing switching. Additionally, adjusting the channel doping of the p-channel TFT effectively tunes the switching voltage, as shown in Fig. 1. References [1] Y. A. Huang, C. Y. Liang, K. P. Peng, K. M. Chen, G. W. Huang, P. W. Li, and H. C. Lin, “A unique approach to generate self-aligned T-Gate transistors in counter-doped poly-Si with high etching selectivity and isotropy,” IEEE Electron Device Lett., vol. 41, no. 3, pp. 397–400, [2] C. K. Lee, K. M. Chen, G. W. Huang, P. W. Li, and H. C. Lin, “Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain,” Jpn. J. Appl. Phys., vol. 62, SC 1009-1–5, Dec. 2022, DOI: 10.35848/1347-4065/aca773. Figure 1